ECE 3270/3271 – Digital Computer Design

Course Code

ECE 3270 / 3271

Level

Undergraduate

Credits

4 (3 lecture + 1 lab)

Semester

Fall 2026

Lecture

Tu Th 12:30 – 1:45 PM

Location

TBA

Office Hours

TBA

Instructor

Dr. Uma Tida

Course Overview

Digital Computer Design covers the design, description, and verification of digital systems using a hardware description language, and their realization on programmable logic. The course moves from combinational modeling and arithmetic circuits through sequential elements, registers, counters and finite state machines, and culminates in the design of a datapath and control unit for a simple processor.

The paired lab section (ECE 3271) is a hands-on sequence: every concept introduced in lecture is written in Verilog, simulated against a testbench, synthesized, and run on an FPGA board. Students finish the semester having built and debugged real hardware rather than only having analyzed it on paper.

Topics Covered

Module 1 — Combinational Design in Verilog

Verilog modeling concepts and design flow
Adders and arithmetic circuits
Multi-output and multi-level circuits
Tasks, functions, and testbenches

Module 2 — Sequential Logic and State

Latches and flip-flops
Registers, shift registers, and counters
Behavioral modeling and timing constraints
Counters, timers, and a real-time clock
Finite state machines
Sequential design using ASM charts

Module 3 — Processor Datapath and SoC

IP catalog and the architectural wizard
Integrated logic analyzer and on-chip debug
IP integrator and block design
Datapath and control unit design
A simple processor
Bit-pair recoded multiplier

Learning Objectives

Students who complete this course will be able to:

Model combinational and sequential hardware in Verilog
Write testbenches and verify a design by simulation
Design finite state machines from a specification
Partition a system into datapath and control
Apply timing constraints and read synthesis reports
Implement and debug a design on an FPGA board

Laboratory Sequence (ECE 3271)

The lab meets weekly and follows the lecture. Each lab is written, simulated, synthesized, and demonstrated on hardware.

Week	Lab	Deliverable
Module 1 — Combinational Design in Verilog
1	Modeling concepts and toolchain setup	Simulation waveform
2	Addition: ripple-carry and carry-lookahead	Synthesis report
3	Multi-output circuits	Board demo
4	Tasks, functions, and testbenches	Testbench + coverage
Module 2 — Sequential Logic and State
5	Latches and flip-flops	Timing analysis
6	Registers and counters	Board demo
7	Behavioral modeling and timing constraints	Constraint file
8	Counters, timers, and real-time clock	Board demo
9	Finite state machines	State diagram + RTL
10	Sequential system design using ASM charts	ASM chart + RTL
Module 3 — Processor Datapath and SoC
11	Architectural wizard and IP catalog	Block design
12	Integrated logic analyzer and on-chip debug	Captured trace
13	Simple processor: datapath and control	Working processor
14	Bit-pair recoded multiplier	Final demo

Lab materials. The lab exercises follow the open FPGA/SoC/Verilog/HLS lab collection maintained by Prof. Qing (Ken) Yang (University of Rhode Island) and Prof. Tao Wei (Clemson University), available at uri-nextlab.github.io/ParallelProgrammingLabs. That collection draws in turn on AMD/Xilinx university workshops and on course material from UCSD, Clemson, and Georgia Tech.

Grading Scheme

TBA — weighting for homework, labs, exams, and the final project will be posted with the syllabus.

Textbooks & References

Lab reference: Verilog Labs — URI NextLab / Clemson
Tool reference: AMD/Xilinx Vivado Design Suite user guides
Required text: TBA

← Back to Teaching