Research

Monolithic 3D integration stacks multiple device layers on a single die using ultra-thin inter-tier dielectrics, enabling nanoscale Metal Inter-Layer Vias (MIVs) — 1,000× smaller than TSVs. This unlocks unprecedented transistor density but demands entirely new EDA flows that conventional tools cannot provide.

Our NSF CAREER-funded research (2025–2030) develops process-technology-aware EDA frameworks accounting for MIV coupling effects, back-gate transistor opportunities, and heterogeneous substrate integration.

• Process-aware placement & routing with MIV keep-out-zone shielding
• Back-gate transistor utilization — 21% standard cell area reduction
• Dual-purpose MIV exploitation for on-chip memory and logic
• Thermal and thermo-mechanical stress modeling across stacked tiers
• OpenROAD integration for open-source M3D EDA flows

Modern ASIC design faces an engineering cost explosion — a complex SoC requires hundreds of engineers and years of effort. ACE² harnesses graph neural networks, reinforcement learning, and large language models to dramatically accelerate the ASIC design process from RTL through physical implementation.

Our SysVCoder framework fine-tunes Qwen 7B for Verilog RTL generation, achieving state-of-the-art Pass@1/Pass@5. A GAT+PPO reinforcement learning agent drives timing-aware cell placement via OpenROAD.

• GAT + PPO RL agent for timing-aware cell placement via OpenROAD
• SysVCoder: >30% improvement in Pass@1/Pass@5 over SOTA Verilog LLMs
• HierarchicalTB: automated testbench generation for hierarchical designs
• ML-assisted magnetic-core inductor design with MINLP solver integration
• Graph neural network representation of gate-level netlists for timing prediction

GPU compute density for LLM inference has improved only ~15% over 2.5 years (H100 → B200), while model sizes have grown orders of magnitude. Purpose-built ASIC accelerators offer the only viable path to efficient LLM deployment at scale and on edge devices.

We design custom Compute-in-Memory (CIM) ASIC architectures for LLM acceleration, co-optimizing quantization, compression, and RAG hardware with SRAM-based dataflow to achieve significant gains in MIPS and energy efficiency.

• CIM ASIC architectures for transformer attention and feed-forward layers
• Joint compression + quantization: <20 min training on edge hardware
• RAG hardware integration for domain-specific LLM acceleration
• MIPS-optimized dataflow with minimal data movement overhead
• Cross-layer co-design bridging algorithm sparsity with ASIC floorplanning