Hardware Design for Machine Learning

Course Overview

This course bridges the gap between machine learning theory and hardware implementation. Students learn to design custom accelerators for neural networks, targeting energy-efficient and high-throughput deployments on ASICs and FPGAs. The 677 (graduate) section includes a deeper treatment of research literature and an independent project on accelerator design or deployment.

Topics Covered

• Neural Network Foundations for HW Design
• Dataflow Architectures and Systolic Arrays
• Quantization-Aware Design
• Sparse and Compressed Neural Networks
• FPGA-Based Accelerator Prototyping
• Edge-AI Deployment Strategies
• Memory Bandwidth and On-Chip Storage
• Transformer and LLM Hardware
• Power and Thermal Management
• Case Studies: TPUs, NPUs, Custom ASICs

Course Objectives

Students completing this course will be able to: (1) map neural network computations to hardware dataflows; (2) design and evaluate accelerator architectures for throughput, energy, and area; (3) implement and test a DNN accelerator prototype on FPGA; and (4) critically read and present research papers on ML hardware.